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Espressif Systems /ESP32-P4 /H264_DMA /IN_INT_ST_CH5

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Interpret as IN_INT_ST_CH5

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IN_DONE_CH5_INT_ST)IN_DONE_CH5_INT_ST 0 (IN_SUC_EOF_CH5_INT_ST)IN_SUC_EOF_CH5_INT_ST 0 (INFIFO_OVF_L1_CH5_INT_ST)INFIFO_OVF_L1_CH5_INT_ST 0 (INFIFO_UDF_L1_CH5_INT_ST)INFIFO_UDF_L1_CH5_INT_ST 0 (FETCH_MB_COL_CNT_OVF_CH5_INT_ST)FETCH_MB_COL_CNT_OVF_CH5_INT_ST

Description

RX CH5 interrupt st register

Fields

IN_DONE_CH5_INT_ST

The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
IN_SUC_EOF_CH5_INT_ST

The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
INFIFO_OVF_L1_CH5_INT_ST

The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
INFIFO_UDF_L1_CH5_INT_ST

The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
FETCH_MB_COL_CNT_OVF_CH5_INT_ST

The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd